1. Field of the Invention
This invention relates to the field of synchronous telecommunications networks, and particularly to the generation of slave clocks that are synchronized to a reference clock source for use in such a network.
2. Description of the Related Art
Large telecommunications networks consist of switching engines and transmission lines. Digital networks support services whose signals may be either analog or digital in origin, with analog signals carried through a digital network by representing them as a sequence of digital words.
Two main types of digital telecommunications networks exist: circuit-switched and packet-switched. Circuit-switched networks evolved to carry real-time services, such as voice, while packet-switched networks evolved to carry data-oriented services. Until recently, separate networks were needed for circuit-switched and packet-switched architectures, and large differences were to be found in the elements of equipment used to construct them. This separation is costly in terms of equipment cost, maintenance, and operation of the networks. It has been recognized for some time that efficiencies could be realized if both types of architecture could co-exist on the same network, but a number of hurdles must first be overcome.
For many years, voice traffic has been dominant and has led the circuit-switched networks to dwarf packet-switched networks. Although non-voice services are growing rapidly, the size of the circuit-switched networks must be considered when trying to make a common network. Due to the large amount of circuit-switched equipment that is already in place, using such a network for both voice and data traffic is desirable. However, a relatively high error-rate is inherent in the make-up of circuit-switched networks, which is unsuitable to the demands of packet-based communications.
One way in which voice or data traffic can become corrupted is when samples are lost due to consecutive switches operating at slightly different rates. The rate of transmission through a first switch is determined by the speed of the switching clock provided to that switch. Similarly, the rate of consumption of signals at the input of a second switch is determined by the speed of the switching clock provided to the second switch. When the rate of consumption matches the rate of arrival, the switches operate error-free. However, when the rate of consumption differs from the rate of arrival, the switches generate errors, the cumulative effect of which can become quite large as a signal propagates through a network. Buffers can be placed on the inputs of switches to accommodate differences in transmission rates, but these introduce delays which can also have a detrimental effect on the quality of the received signal.
These difficulties make the use of circuit-switched networks to carry packets problematic. Because of the need to re-transmit packets containing errors, the throughput of a packet-switched network is significantly reduced when even a small error rate is present. Uncorrupted transmission of digital signals through and between switches depends upon the relative accuracy with which the individual switch clocks operate. To reduce error-rates in the switches, it is necessary to run the switches at the same rate. Modern communications networks typically have a hierarchal clock distribution structure to distribute a common clock to all switches. Switches can synchronize to a clock from either a higher-level switch or from a peer-level switch, if needed. Each switch is therefore a source of a clock signal for neighboring switches. Each time a clock is regenerated, the new clock is termed to be a "slave" of the clock from which it was derived (a "master" clock).
Clock distribution networks are prone to occasional failures, and keeping the network operating during an outage is a prime requirement. For this reason, the distribution network must have some degree of resilience and self-healing. Three operating modes have been identified in the various standards that govern large synchronous telecommunications networks: locked mode, holdover mode and free-running mode. These modes reflect the three stages of operation of a distribution network element. On power-up, the clock generation hardware enters the "free-running" mode. In this mode, the local slave clock is intended to be stable and close to the nominal network rate, but is not required to be synchronous. The free-running mode is usually retained until a good synchronization source is detected from a higher-level or peer-level element. The "locked mode" of operation is used when a good synchronization source has been detected, at which point the local slave clock is driven into synchronization with the incoming clock. If the synchronization source fails, the clock generator enters the "holdover mode". In this mode, the local slave clock is generated to be as close as possible to the last-known-good value of the incoming clock. This requires some stored history of the behavior of the incoming clock. Clock generation reverts to locked mode when a good synchronization source is detected.
Thus, the slave clock generator is a critical item of equipment in a clock distribution network. This system has to detect the presence and absence of synchronization sources, generating the slave clock either in synchronism with the best source, when present, or in very close approximation to it, when absent. Traditionally, the performance requirements imposed by the various telecommunications networks standards (chiefly ITU-T G.783, G.811-813, Bellcore GR-253-CORE, and ETSI 300462 (parts 1 to 6)) have been met using a voltage-controlled oscillator (VCO). The VCO is controlled by a control algorithm implemented in software and running on a microprocessor, which takes inputs from a number of sensors (e.g., temperature and voltage) and a phase comparator and generates a control voltage that causes the VCO to mimic a selected master reference source, thereby generating a slave clock.
There are several drawbacks to the use of a VCO for slave clock generation, however. Though a VCO-based system could, in principle, be integrated onto a single semiconductor substrate, its use of disparate components does not make this task easy. The operation of embedded microprocessors, instruction and data memories, and assorted other digital functions, are not compatible with the operation of sensitive analog components such as comparators and VCOs. Furthermore, the electrical noise generated by the digital components can degrade the operation of the analog components. In particular, noise appearing on the control input of a VCO leads to variations in the output frequency, otherwise known as jitter. Maximum jitter specifications for this application are typically tight, meaning that only very low levels of noise can be tolerated. Noise control is difficult when digital components are mounted close to analog components, as would be necessary with an fully integrated implementation.
Noise problems are also present in discrete VCO implementations, but precautions taken in the circuit board layout can render a design workable. However, these precautions are dependent upon various factors which are frequently out of the control of the designer of the slave clock generator. This makes each implementation unique, because the layout has to be carefully considered each time a new design is implemented. Using discrete components can also lead to unacceptable levels of space and power consumption. Finally, both discrete and integrated VCO-based systems require extensive calibration procedures needed to provide the temperature compensation necessary to meet the performance specifications. This is time-consuming and expensive.